基于DM642的视频通信系统——采集处理播放子系统的设计与实现/

2019-05-04 01:07:54

video acquisition 视频 processing DM642EVM



随着信息时代的到来,信息处理技术特别是视频信息处理技术得到了飞速的发展,视频通信系统已经广泛应用于视频会议、视频监控等方面。在开发视频通信系统时,遇到的最大困难就是对视频数据信息的采集、播放和算法处理,这主要是因为在对大量的数据信息进行处理时,视频通信系统大多要求保证系统的高速性、稳定性和灵活性。因此,构建用于采集、播放和算法处理的子系统或终端系统,已经成为用于局域网和广域网上实际应用系统设计的关键所在,日益引起人们的关注。
本文提出的基于DM642EVM板的视频采集处理播放子系统的设计与实现方案,采用了嵌入式技术和多路技术,并从采样技术入手,软件降低采样率,使得系统能够根据网络状态提供适当格式的图像,消除欠采样噪声,而且通过运动检测来控制帧率,从而可以有效的节省传输带宽,达到根据网络情况自适应地提供多种QoS服务等级的目的。
TI公司的DM642是基于第二代高效先进的VelociTI超长指令字体系结构设计出来的,这类DSPs是数字媒体应用的最佳选择。DM642的DSP内核是C64x系列的32位定点DSP,在时钟频率为600MHz时,处理速度为4800MIPS。DM642使用两级cache结构:L1级cache由16K的L1程序存储器(L1P)和16K的L1数据存储器(L1D)组成,L2级cache大小为256K字节,可以由程序和数据空间共享。外围设备包括:三个可配置视频口;一个10/100M比特/秒的以太网媒体接入控制器(EMAC);一个数据输入/输出管理(MDIO)模块;一个VCXO内插控制端口(VIC);一个多通道缓冲音频串口(McASP0);一个I2C总线模块;两个多通道缓冲串口(McBSPs);三个32比特通用定时器;一个用户自定义16比特或32比特主机接口(HPI16或者HPI32);一个外设部件互连(PCI)和一个64比特的外部存储器接口(EMIFA),可以与同步/异步存储器或其他外设接口。
在硬件实现原理上,根据DM642EVM板的硬件特点,通过编写程序,并利用相关库文件(CSL和BSL),读写I2C总线,对SAA7115芯片进行配置。可以提供两路的视频采集及NTSC和PAL两种制式彩色图像,实现板卡扩展外设摄像头的4CIF/CIF格式采集,并能根据网络条件的反馈信息,对采集到的图像重新采样,获得CIF/QCIF/SQCIF/用户自定义等格式的图像,从而降低每帧像素数。播放端同样需要对SAA7105芯片进行参数设置,提供当前网络状态要求下的尺寸图像和插值到CIF格式的图像,并在板卡扩展外设电视机上四分屏显示。
在软件实现原理上,本文主要通过编写嵌入式软件程序,使用驱动模块进行设置,控制DM642EVM板上SAA7115和VP0视频口,实现基于DM642EVM的视频采集功能,把采集的图像暂存到采集缓冲区内。通过运动检测模块与预先设定的参考帧比较(首次不做比较),如果没有检测到图像运动,则系统采集下一帧,不做其他处理;如果有运动,首先更新系统帧,然后根据网络带宽信息的反馈分析,来控制视频图像每帧像素数,即通过视频采集及软件降采样模块对原始采集图像进行软件降采样,控制采集缓冲区输出的图像格式。图像格式可在4CIF/CIF/QCIF/SQCIF和用户自定义五种格式间变化,提供多种QoS等级的视频业务。之后,判断图像是否欠采样,若是,则通过欠采样处理程序模块,消除采样率软降解中生成的欠采样噪声,来达到低采样率下支持较好的图像质量的目的;否则,越过欠采样处理程序模块。然后,把图像数据复制成两份,其中一份图像数据再通过压缩编码模块做H.263压缩编码,存入网络发送缓冲区,通过网络传输程序模块传送到广域网/局域网中的远端PC机做H.263解码并显示;另一份则通过视频播放程序模块及插值和画中画模块在DM642EVM板的扩展外设电视机上四分屏显示。按照同样的原理,本系统可以支持两路的视频。
本文提出的系统方案的设计与实现细节主要包括:(1)视频采集处理和播放实现原理研究与系统设计;(2)DM642板上视频口及相关器件驱动设计;(3)TI参考框架5(RF5)理论的研究及以RF5为基础建立系统的应用程序;(4)设计便于系统处理和内部交互的系统内部数据结构,且这些数据结构要遵循ITU-R BT.656标准;(5)多任务的程序设计思想,保证任务间的正确通信;(6)根据硬件情况,至少支持两路视频采集、播放和算法处理;(7)研究视频帧图像的多格式软件降采样算法处理技术;(8)实现本地插值显示,支持输出端的分区显示;(9)研究运动检测处理算法,控制帧率,进一步保证有效带宽;(10)支持画中画显示功能;(11)支持NTSC制式和PAL制式;(12)研究消除欠采样噪声算法原理,并实现消除欠采样噪声算法处理功能等。
本文提出的系统设计与实现方案,实现了高速的、稳定的、灵活的嵌入式视频采集处理播放平台,可以作为独立的视频通信系统,高速而稳定的持久运行,达到了设计的要求。
基于DM642EVM设计和实现视频采集处理播放子系统/终端系统技术是一个新兴的研究领域,而本文提出的视频采集处理播放系统并没有完全开发出DM642EVM平台的巨大潜能,还有许多未触及的研究课题,例如,可以考虑把H.264压缩算法移植到DM642EVM平台上以进一步提高系统的性能、采用PCI方式把视频终端系统的采集数据存储到大容量硬盘上以及在视频基础上进一步支持音频的应用,另外,现有技术也可能需要改进和提高。可以说基于DM642EVM设计和实现视频采集处理播放系统技术具有很好的研究前景,也是一个充满活力且有待开拓的研究领域。本文在最后对基于DM642EVM设计和实现视频采集处理播放系统技术的发展作了展望。



Along with the arriving of information age, the technologies of information processing, especially the video information processing, have been developed rapidly. The video communication system has been widely applied in video conference, video monitoring and other fields. When developing the video communication system, the hugest obstacle is the video acquisition, display and algorithm processing, because the video communication system need to be high-speed, steady and flexible, while handling the mass video data. Therefore, constructing the system for video acquisition, processing and display is becoming the key point of the actual application system design in WAN/LAN, and has drawn great attention.
This dissertation proposes a design and implementation scheme of video acquisition, processing and display sub-system/terminal system based on DM642EVM board. Embedded technologies, multi-way technologies and sampling technologies are used to reduce the sampling rate by software, so that the system can provide appropriate image format according to the condition of network and can eliminate aliasing noise. The system also uses motion detection to control the frame rate. Therefore, the system can save transmission bandwidth effectively and design to provide multiple degrees QoS according to the network condition.
The DM642EVM, which is based on the second-generation efficient and advanced VelociTI very long instruction word architecture, is developed by Texas Instruments, and using such DSPs is an excellent choice for digital media applications. The DSP core of the DM642 is 32-bit fixed-point DSPs of C64x, with the performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600MHz. The DM642 uses a two-level cache-based architecture, Level 1 cache is composed of a 16-Kbit L1P (level 1 program cache) and a 16-Kbit L1D (level 1 data cache), Level 2 cache consists of 256-Kbit memory space that is shared between program and data space. The peripheral elements include: three configurable video ports, a 10/100 Mb/s Ethernet MAC (EMAC), a management data input/output (MDIO) module, a VCXO interpolated control port (VIC), one multichannel buffered audio serial port (McASP0), an inter-integrated circuit (I2C) Bus module, two mulitchannal buffered serial ports (McBSPs), three 32-bit general-purpose timers, a user-configurable 16-bit or 32-bit host-port interface (HIP16/HPI32), a peripheral component interconnect (PCI), and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.
With regard to the hardware, according to the hardware characteristic of DM642EVM, the program is composed and the library files (CSL and BSL) are used to configure the SAA7115 chip through I2C bus. The system can provide two-way video acquisition and NTSC/PAL color image, and implements the board extending camera’s acquisition of 4CIF/CIF format. Besides, it can resample the image according to the feedback information of the network condition, so the CIF/QCIF/SQCIF/user-defined image can be obtained to reduce the pixel number in one frame. When displaying, it is also necessary to configure SAA7105 chip, thus the system can provide both the demanding size image of current network condition and the CIF size image after interpolation, then display these images in four divisional areas of screen through the board extending TV.
With regard to the software, through the driver module, this system uses embedded software programs to control SAA7115 chips and VP0 video port, so the system can realize the video acquisition function based on DM642EVM and store the acquisition frame to acquisition buffers. Then the current acquisition frame is compared with the reference frame (isn’t compared at the first time) by motion detection module, if there is no motion detected, the system just acquire the next frame and will not do any process. Otherwise, the reference frame will be updated firstly, and then the system controls the pixel number of one frame according to the feedback information of the network condition. In other words, through video acquisition module and software resampling module, the system can control the output image format of acquisition buffer. The image can vary among 4CIF/CIF/QCIF/SQCIF/user-defined formats, and video services of the multiple degrees QoS are supplied. After that, the fact whether there is aliasing noise in the image will be challenged, if the aliasing noise exists, through aliasing noise eliminating module, the system can eliminate the aliasing noise generated by software resampling, and support the ability of providing high quality at low sampling rate condition. Otherwise, the system bypasses the aliasing noise eliminating module. And then, the system copies the image data twice, one copy is handled by H.263 compression algorithm in the compressing module, then stored in network sending buffer and transferred to remote PC in LAN/WAN by network transferring module,and the data will be decompressed and displayed there. Through the video display module and interpolation/PIP module, another copy is displayed in four divisional areas of the screen on DM642EVM’s on-ship peripheral TV. As the same principle, this system can support two-way video acquisition, processing and display.
The design and implementation details of the system scheme proposed by this dissertation includes: (1) study and design the system of video acquisition, processing and display based on DM642EVM board, (2) design the drivers of video port and relative chips on the DM642EVM board, (3) study the theory of TI reference framework 5 and construct application program on RF5, (4) design the system inside data structure which is convenient for system processing and inter-active. The data must follow the ITU-R BT.656 video standard, (5) study how to design multi-task program, and guarantee the correct communication among tasks, (6) support two-way video’s acquisition, display and algorithm processing according to the hardware condition, (7) study the processing algorithm about software resampling multi-format of video frames, (8) implement the function of local interpolated image display, and display the images in four divisional areas of screen through TV, (9) study the motion detect processing algorithm to control frame rate, guarantee the valid bandwidth further, (10) support the function of picture in picture (PIP) display, (11) support NTSC and PAL, (12) study the processing algorithm of aliasing noise and eliminating it and so on.
A high-speed, steady and flexible embedded video acquisition, processing and display system has been implemented through the scheme proposed by this dissertation. It has achieved the main functions of the design requirement, and can run high-speedily and steadily as an independent video system.
The technology of design and implement video acquisition, processing and display system based on DM642EVM is a new research field, the system proposed by this dissertation has not fully developed the huge potential of DM642EVM yet. There are still some areas that this dissertation didn’t touch, for example, how to transplant H.264 algorithm on DM642EVM to promote the performance of the system, how to store the data acquired by this system to large capacity hard disk through the PCI mode and how to support audio application in this system. Moreover, the current technology may also need to be improved and advanced. The technology of design and implement video acquisition, processing and display system based on DM642EVM has a promising research future, and it is also a vigorous and exploitable field. This dissertation makes an outlook for the technologies of design and implements video acquisition, processing and display system based on DM642EVM board in the end.