In situ fault detection of wafer warpage in microlithography

2020-02-16 16:10:15

fault processing detection reliability warpage

责任者: Weng Khuen Ho;Tay, A.;Ying Zhou;Kai Yang 单位: Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore 来源出处: IEEE Transactions on Semiconductor Manufacturing(IEEE Trans. Semicond. Manuf. (USA)),2004/08/,17(3):402-7 摘要: Wafer warpage is common in microelectronics processing. Warped wafers can affect device performance, reliability and linewidth control in various processing steps. We proposed in this paper an in situ fault detection technique for wafer warpage in microlithography. Early detection will minimize cost and processing time. Based on first principle thermal modeling, we are able to detect warpage fault from available temperature measurements. Experimental results demonstrate the feasibility and repeatability of the approach. The proposed approach is applicable to other semiconductor substrates 关键词: ab initio calculations;fault diagnosis;integrated circuit reliability;integrated circuit testing;nanolithography;semiconductor process modelling;in situ fault detection;wafer warpage;microlithography;microelectronics processing;device performance;reliability;linewidth control;first principle thermal modeling;temperature measurements;semiconductor substrates