Direct tunneling memory using ultra-thin oxide and deca-nano floating gate struc

2019-06-23 04:11:52

tunneling semiconductor gate oxide DTM

责任者: Usuki, Tatsuya;Horiguchi, Naoto;Goto, Kenichi;Tanaka, Takuji;Futatsugi, Toshiro;Sugii, Toshihiro;Yokoyama, Naoki 单位: Fujitsu Lab Ltd, Atsugi, Jpn 来源出处: Superlattices and Microstructures,2000,28(5-6):401-406 摘要: Direct tunneling memory (DTM) with nano-scale gate oxide accomplished low-voltage operation and full compatible process with MOSFET. DTM has a leakage stop barrier and sidewall control gate (CG) which prevent the overlap between a floating gate (FG) and source/drain (SD) extensions. In this work, improved DTM structure overcomes the first demonstration. To design DTM, we also developed a new simulator which considers direct tunneling phenomena and quantum effect at the oxide interface. The simulation shows that DTM has sufficient tolerance against oxide thickness (Tox) fluctuations. 关键词: Semiconductor storage;Semiconductor device structures;Nanotechnology;Semiconductor device models;Computer simulation;Quantum theory;Leakage currents;MOSFET devices;Direct tunneling memory;Ultrathin oxide;Nanofloating gate